VITA

VITA
Open standards, open markets

VITA is an incorporated, non-profit organization of vendors and users having a common market interest in real-time, modular embedded computing systems. Accredited as an American National Standards Institute (ANSI) developer and a submitter of Industry Trade Agreements to the IEC, the VITA Standards Organization provides its members with the ability to develop and to promote open technology standards.

VME Technology adheres to the open system architecture definition of real-time, modular embedded computing systems. Intensive development and field deployed systems have proven out the concept of VMEbus. The developers within the VMEbus community are committed to technology excellence through evolutionary changes.

ANSI/VITA 1 is the original VMEbus specification for 8-, 16-, 32, and 64-bit parallel-bus computer architectures that can implement single and multiprocessor systems. The mechanical specifications of boards, backplanes, subracks, and enclosures are based on IEC 297 and IEEE 1101.1 specifications, also known as the Eurocard form factor. ANSI/VITA 1.1 now supports a 160 pin connector, a P0 connector, geographical addressing, voltages pins for 3.3V, a test and maintenance bus, and EMI, ESD, and front panel keying per IEEE 1101.10.

FPGA Mezzanine Card, or FMC, as defined in VITA 57 provides a specification describing a new I/O mezzanine module. The module will connect to, but not be limited to, 3U and 6U form factor cards. FMC modules use a smaller form factor compared with PMC or XMC modules, and assume connection to an FPGA or other device with reconfigurable I/O capability.

ANSI/VITA 1.5, 2eSST, is an extension of the ANSI/VITA 1-1994, VME64 and ANSI/VITA 1.1-1997, VME64x standards. It defines a new transfer protocol, based upon source synchronous concepts, that permits the VMEbus to operate at rates up to 320MB/s. As technology improves, this rate can be extended to higher levels.

ANSI/VITA 31.1, Gigabit Ethernet on VME64x, defines a pin assignment and interconnection methodology for implementing a 10/100/1000BASE-T Ethernet switched network on a VME64x backplane via a P0 connector. This is the first generation of serial switched fabric solutions implemented in VMEbus backplanes. ANSI/VITA 31.1 on P0, as well as several other serial schemes, all work with the VME32, VME64 and VME2eSST configurations.

VXS, or VMEbus Switched Serial (ANSI/VITA 41) combines parallel VMEbus with enhancements to support serial switched fabrics including PCI Express and RapidIO over a new high speed P0 connector. Backward compatibility is maintained with existing backplanes that do not have a conflicting P0 scheme. Combining the VME2eSST parallel bus with serial switch fabric technologies for multi-point, high-speed data transfers creates choices for embedded computing designs of all types.

VPX (ANSI/VITA 46) breaks out from the traditional connector scheme of VMEbus to merge the latest in connector technology with the latest in bus technology. VPX combines best-in-class technologies to assure a very long technology cycle similar to that of the original VMEbus solutions. Traditional parallel VMEbus continues to be supported by VPX through bridging schemes that assure a solid migration pathway.

XMC (VITA 42) defines an open standard for supporting high-speed, switched interconnect protocols on the popular PMC form factor. It adds connectors for the high-speed interconnects while retaining the main features of the PMC specification, staying within the height. It provides better definition for carrier cards, and allows for optional configuration without PMC connectors using only the high-speed connectors.

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